Intel used the stage of Hot Chips 2025 in Cupertino to unveil its most ambitious Xeon yet: Clearwater Forest, an all-E-core server processor built on the company’s next-generation 18A process node. Packing 288 efficiency cores (E-cores) per socket and scaling up to 576 cores in dual-socket systems, the new Xeon represents both a technological milestone and a strategic counterpunch in the battle for hyperscale data centers. Scheduled to ship in 2026, Clearwater Forest is Intel’s showcase of density, power efficiency, and advanced packaging innovation.
Key Specifications at a Glance
- Core Count: 288 E-cores per socket (576 in dual-socket configurations)
- Process: First Xeon built on Intel’s 18A node with RibbonFET and backside power delivery
- Architecture: New Darkmont efficiency cores with ~17% IPC uplift vs Crestmont
- Cache & Bandwidth: Up to 1,152 MB last-level cache, doubled L2 cache bandwidth, 12 channels of DDR5-8000 memory
- Packaging: Multi-die design with 3D Foveros stacking and EMIB interconnects
- Compatibility: Works with existing Xeon 69xxE/P platforms, broad PCIe and CXL support
Darkmont Cores: Modest IPC, Massive Parallelism
At the heart of Clearwater Forest are Intel’s Darkmont E-cores, designed with a wider decode engine (3×3), a deeper out-of-order window, and enhanced execution ports to push throughput higher. Each cluster of four cores shares 4 MB of L2 cache, doubling the L2 bandwidth over the outgoing Sierra Forest.
The result: ~17% higher IPC than Crestmont cores, scaled across hundreds of cores for high-density workloads. Unlike AMD’s EPYC Bergamo, which chases single-thread strength with SMT and wide vector units, Intel’s Clearwater design goes all-in on scale — aiming to maximize total throughput and perf-per-watt.
Architectural Packaging: Foveros Meets EMIB
The physical design underscores Intel’s leadership in packaging. Clearwater Forest uses:
- 12 compute chiplets on Intel 18A stacked over three Intel 3 base tiles
- Two I/O tiles on Intel 7 at the package’s edges
- Foveros Direct 3D stacking and EMIB bridges to tie everything together
This approach allows Intel to pack more cores and larger caches into a single socket, all while maintaining signal integrity and reducing power delivery losses thanks to backside power delivery.
Efficiency & Scale for the Data Center
Intel positions Clearwater Forest as the natural successor to Sierra Forest, designed to consolidate workloads in hyperscale environments. By offering 3.5x performance per watt improvements over previous Xeons, Clearwater promises to reduce server counts, lower power bills, and deliver over 1,000 vCPUs per rack in dual-socket deployments.
This positions Clearwater as Intel’s answer to AMD’s Bergamo and future Zen 6 server chips, though the two approaches differ fundamentally. Where AMD emphasizes flexibility and strong single-thread performance, Intel doubles down on massive core counts and power efficiency.
A Defining Moment for Intel’s 18A Node
Clearwater Forest is also a proving ground for Intel’s 18A process technology, featuring RibbonFET gate-all-around transistors and backside power delivery. If the node delivers as promised, Intel will regain ground against TSMC in the most competitive process era of the past decade, a critical step for both its foundry business and its position in the server CPU market.
Outlook
Clearwater Forest represents more than just another Xeon SKU; it’s a strategic bet. By combining 288 Darkmont E-cores, massive cache structures, DDR5-8000 memory bandwidth, and state-of-the-art packaging, Intel is signaling to hyperscalers that it can compete head-to-head on efficiency and density.
Slated for release in 2026, Clearwater Forest will be one of the most closely watched CPUs in the data center race. While AMD’s EPYC remains a formidable rival and Arm-based designs continue to gain traction, Intel is betting that scale, efficiency, and process leadership will redefine what a Xeon can be.
