A new network-on-chip (NoC) IP promises to significantly accelerate chip development by using AI to automate key processes and minimize wire length. This leads to lower power consumption in system-on-chip (SoC) designs. Arteris, the company behind the “FlexGen” interconnect IP (which they’re calling a “smart NoC”), claims it can deliver a tenfold increase in productivity, shrinking design iteration times from weeks to days.
The Growing Complexity of Chip Design
Modern chips are incredibly complex, packed with billions of wires. As chips become complex, so does the challenge of designing the interconnects that link all the components.
Today’s SoCs often include many separate NoC instances, requiring multiple design iterations. This complexity has outgrown the capabilities of manual design methods, creating a need for intelligent automation.
FlexGen: AI-Driven Automation for Faster Development
According to Arteris, much of the SoC interconnect design process is still manual, even with technological advancements. FlexGen aims to change that by automating the design and configuration of NoC IP, significantly reducing the time and effort required.
How FlexGen Works
FlexGen leverages existing NoC IP technology as its foundation but adds an AI layer to automate the infrastructure. This automation reduces manual work and enables higher-quality configurations that rival or surpass those achieved through manual design. The key benefit is faster development cycles and potentially more efficient chips.
Source:edn.com
