Next-generation PCI Express set to deliver 1TB/s bi-directional bandwidth with advanced protocol and power efficiency enhancements
PCI-SIG®, the consortium responsible for the widely adopted PCI Express® (PCIe®) standard, today announced the development of the PCIe 8.0 specification, marking a significant milestone in the evolution of high-speed interconnect technologies. The upcoming spec will double the data rate of PCIe 7.0, reaching 256 GT/s per lane and offering up to 1 TB/s of bi-directional bandwidth via a x16 configuration.
Building upon PAM4 signaling, Forward Error Correction (FEC), and Flit Mode encoding from previous generations, PCIe 8.0 will introduce protocol enhancements for increased real-world bandwidth and power efficiency. The consortium is also evaluating new interconnection and connector technologies to address signal integrity, latency, and power delivery challenges, all while maintaining backwards compatibility with existing PCIe implementations.
“PCIe technology continues to serve as the backbone of data-intensive innovation,” said Al Yanes, PCI-SIG President and Chairperson. “With PCIe 8.0, we are enabling scalable performance for next-gen AI/ML, HPC, edge computing, quantum, and automotive applications.”
Key Features and Objectives of PCIe 8.0 Specification:
- 256.0 GT/s raw bit rate per lane
- Up to 1 TB/s bi-directional bandwidth via x16 configuration
- Protocol enhancements to maximize throughput and reduce latency
- Continued emphasis on lowering power consumption
- Evaluation of new connector technologies to meet signal integrity goals
- Full backwards compatibility with previous PCIe generations
PCIe 8.0 is targeted for release to PCI-SIG members by 2028, enabling the ecosystem to prepare for emerging performance requirements across hyperscale data centers, military/aerospace, and next-gen networking.
